Sonia López, Oscar Garnica, David H. Albonesi, Steven G. Dropsho, Juan Lanchares, José Ignacio Hidalgo: A phase adaptive cache hierarchy for SMT processors. Microprocessors and Microsystems - Embedded Hardware Design 35(8): 683-694 (2011)
Sonia López, Oscar Garnica, David H. Albonesi, Steven G. Dropsho, Juan Lanchares, José Ignacio Hidalgo: Adaptive Cache Memories for SMT Processors. DSD 2010: 331-338
José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo: Characterizing asynchronous variable latencies through probability distribution functions. Microprocessors and Microsystems - Embedded Hardware Design 33(7-8): 483-497 (2009)
Josefa Díaz, José Ignacio Hidalgo, Francisco Fernández, Oscar Garnica, Sonia López: Improving SMT performance: an application of genetic algorithms to configure resizable caches. GECCO (Companion) 2009: 2029-2034
José Manuel Colmenar, Noelia Morón, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo: Modelling Asynchronous Systems using Probability Distribution Functions. PDP 2008: 3-11
Guadalupe Miñana, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar, Oscar Garnica, Sonia López: Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders. IET Computers & Digital Techniques 1(2): 113-119 (2007)
Sonia López, Steven G. Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares: Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors. PACT 2007: 416
Sonia López, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares: Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches. HiPEAC 2007: 136-150
José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López: Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart. DSD 2006: 423-432
Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar: A Power-Aware Technique for Functional Units in High-Performance Processors. DSD 2006: 456-459
José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López: Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions. Euro-Par 2006: 495-505
Guadalupe Miñana, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares, José Manuel Colmenar, Sonia López: A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors. PATMOS 2006: 514-523
Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar: Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width. PATMOS 2005: 40-48
Sonia López, Oscar Garnica, José Manuel Colmenar: Enhancing GALS Processor Performance Using Data Classification Based on Data Latency. PATMOS 2004: 623-632
José Manuel Colmenar, Oscar Garnica, Sonia López, José Ignacio Hidalgo, Juan Lanchares, Román Hermida: Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays. PDP 2004: 112-119
Sonia López, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, Román Hermida: Power-Consumption Reduction in Asynchronous Circuits Using Delay Path Unequalization. PATMOS 2003: 151-160
Oscar Garnica, Juan Lanchares, Román Hermida: Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation. Fundam. Inform. 50(2): 155-174 (2002)
Oscar Garnica, Juan Lanchares, Román Hermida: A New Methodology to Design Low-Power Asynchronous Circuits. PATMOS 2002: 108-117
Oscar Garnica, Juan Lanchares, Román Hermida: Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation. ACSD 2001: 167-178
Oscar Garnica, Juan Lanchares, Román Hermida: A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits. DATE 2001: 810