Synchronous digital circuits have several problems as clock skew, power consumption, and others. Asynchronous and self-timed design which uses handshaking protocols instead of a global clock signal can provide a solution for them. One of the main problems of asynchronous design is the lack of automation design tools and environments. In the field of fully asynchronous systems, designers usually develop general purpose processors using high-level description languages like Occam, Tangram, Balsa or VHDL++. Some other works have proposed simulators of asynchronous processor, but they are slightly parameter adaptable and they do not model the asynchronous behavior at the architectural level of design, albeit, these kind of simulators are not able to run standard benchmarks. One of the key questions is how the tool will model the data dependant computation delays of the modules that compose an asynchronous processor. Our research interest lied on two main lines:

First we developed SYM-ASYNC, an architectural simulator for asynchronous superscalar processor modeling, capable to model at the architectural level of abstraction, the data-dependant behavior of the modules by using distribution functions. It is also able to execute any test program compiled for the Alpha ISA, as others synchronous architecture simulators does. Once SYM-ASYNC was working we focused on its parameter adaptation in order to check and test different modifications of the architecture looking for an improvement on the performance or new temperature and power aware self-timed processors. For this purpose we worked on different configurations of Functional Units, memories, etc.

Simultaneous Multithreading (SMT) is a technology aimed at improving the throughput of the processor core by applying Instruction Level Parallelism (ILP) and Thread Level Parallelism (TLP). Nevertheless a good control strategy is required when resources are shared among different threads, so that throughput is optimized. We study the application of evolutionary algorithms to improve the allocation of configurations on the cache hierarchy over a Simultaneous Multithreading (SMT) processor. In this way, resizable caches have demonstrated their efficiency by adapting their configuration according to workload settings, at runtime. Moreover, some methodologies and a number of techniques, such as dynamic resource allocation, have previously been developed to optimize the cache hit behavior, trying to improve global SMT performance. We propose the use of a Genetic Algorithm (GA) to optimize dynamically reconfigurable cache designs. Given that different workloads feature different characteristics and needs, we apply a Genetic Algorithm (GA) for cache designing, in order to obtain a better dynamic configuration that increases the number of instructions per cycle (IPC). Some preliminary obtained results show the feasibility of the approach and the potential of GAs for SMT optimization.

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