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asynchronous_processor_design [2015/01/06 23:21] J. Ignacio Hidalgo		asynchronous_processor_design [2015/01/06 23:21] (current) J. Ignacio Hidalgo
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	Once SYM-ASYNC was working we focused on its parameter adaptation in order to check and test different modifications of the architecture looking for an improvement on the performance or new temperature and power aware self-timed processors. For this purpose we worked on different configurations of Functional Units, memories, etc.		Once SYM-ASYNC was working we focused on its parameter adaptation in order to check and test different modifications of the architecture looking for an improvement on the performance or new temperature and power aware self-timed processors. For this purpose we worked on different configurations of Functional Units, memories, etc.
-	====== Improving SMT Performance: an Application of Genetic Algorithms to Configure Resizable Caches ======	+	====== Improving SMT Performance ======
	Simultaneous Multithreading (SMT) is a technology aimed at improving the throughput of the processor core by applying Instruction Level Parallelism (ILP) and Thread Level Parallelism (TLP). Nevertheless a good control strategy is required when resources are shared among different threads, so that throughput is optimized. We study the application of evolutionary algorithms to improve the allocation of configurations on the cache hierarchy over a Simultaneous Multithreading (SMT) processor. In this way, resizable caches have demonstrated their efficiency by adapting their configuration according to workload settings, at runtime. Moreover, some methodologies and a number of techniques, such as dynamic resource allocation, have previously been developed to optimize the cache hit behavior, trying to improve global SMT performance. We propose the use of a Genetic Algorithm (GA) to optimize dynamically reconfigurable cache designs. Given that different workloads feature different characteristics and needs, we apply a Genetic Algorithm (GA) for cache designing, in order to obtain a better dynamic configuration that increases the number of instructions per cycle (IPC). Some preliminary obtained results show the feasibility of the approach and the potential of GAs for SMT optimization.		Simultaneous Multithreading (SMT) is a technology aimed at improving the throughput of the processor core by applying Instruction Level Parallelism (ILP) and Thread Level Parallelism (TLP). Nevertheless a good control strategy is required when resources are shared among different threads, so that throughput is optimized. We study the application of evolutionary algorithms to improve the allocation of configurations on the cache hierarchy over a Simultaneous Multithreading (SMT) processor. In this way, resizable caches have demonstrated their efficiency by adapting their configuration according to workload settings, at runtime. Moreover, some methodologies and a number of techniques, such as dynamic resource allocation, have previously been developed to optimize the cache hit behavior, trying to improve global SMT performance. We propose the use of a Genetic Algorithm (GA) to optimize dynamically reconfigurable cache designs. Given that different workloads feature different characteristics and needs, we apply a Genetic Algorithm (GA) for cache designing, in order to obtain a better dynamic configuration that increases the number of instructions per cycle (IPC). Some preliminary obtained results show the feasibility of the approach and the potential of GAs for SMT optimization.